The present invention relates to a multistage amplifier in which an input signal is amplified stage by stage and is output.
In a multistage amplifier using a type of semiconductor devices such as field effect transistors (FETs), bipolar junction transistors (BJTs) or hetero junction bipolar transistors (HBTs), an input matching circuit placed on an input side, an output matching circuit placed on an output side and an inter-stage matching circuit placed between the input matching circuit and the output matching circuit are generally arranged so as to bring out the performance of the type of semiconductor devices.
For example, FIG. 1 is a view of an equivalent circuit of a conventional multistage amplifier disclosed in xe2x80x9cTechnical Report of the Institute of Electronics, Information and Communication Engineers (IEICE), MW95-73xe2x80x9d, published in July of 1995. In FIG. 1, 1 indicates an input terminal for receiving a signal. 2 indicates an output terminal for outputting an amplified signal. 3 indicates a front-stage amplifying element for amplifying the signal received in the input terminal 1. 4 indicates a rear-stage amplifying element for amplifying the signal amplified in the front-stage amplifying element 3.
5 indicates an input matching circuit of the conventional multistage amplifier. 6 indicates an inter-stage matching circuit for performing an impedance matching between the front-stage amplifying element 3 and the rear-stage amplifying element 4. 7 indicates a bias circuit. 8 indicates an output matching circuit of the conventional multistage amplifier. 9 indicates a short stub for bias supply. 10 indicates a parallel capacitor. 11 indicates a serial line. 12 indicates a serial capacitor.
Here, each of the front-stage amplifying element 3 and the rear-stage amplifying element 4 is composed of an FET, a BJT, a metal oxide semiconductor field effect transistor (MOSFET), a high electron mobility transistor (HEMT) or an HBT.
Next, an operation will be described below.
When a signal is received in the input terminal 1, the signal is sent to the front-stage amplifying element 3 through the input matching circuit 5, and the signal is amplified in the front-stage amplifying element 3.
Thereafter, the signal amplified in the front-stage amplifying element 3 is sent to the rear-stage amplifying element 4 through the inter-stage matching circuit 6 and the bias circuit 7, and the signal is amplified in the rear-stage amplifying element 4.
Thereafter, the signal amplified in the rear-stage amplifying element 4 is output from the output terminal 2 through the output watching circuit 8.
Here, a function of the inter-stage matching circuit 6 will be described below.
In the inter-stage matching circuit 6, an impedance matching is performed on a certain reference plane between the front-stage amplifying element 3 and the rear-stage amplifying element 4 so as to make a pair of impedances conjugate to each other on both sides of the reference plane. FIG. 2 is an explanatory view showing a general example of matching conditions between the front-stage amplifying element 3 and the rear-stage amplifying element 4 of the conventional multistage amplifier.
As shown in FIG. 2, an output impedance of the front-stage amplifying element 3 is expressed by SYxe2x80x94FET, an impedance (that is, an output load impedance of the front-stage amplifying element 3) on an output side seen from the front-stage amplifying element 3 is expressed by Fout, an input impedance of the rear-stage amplifying element 4 is expressed by Sxxe2x80x94FET, an impedance (that is, an input source impedance of the rear-stage amplifying element 4) on an input side seen from the rear-stage amplifying element 4 is expressed by Fin.
In cases where a small signal operation is performed in the conventional multistage amplifier, an optimum output load impedance xcex93optxe2x80x94out of the front-stage amplifying element 3 agrees with a conjugate complex impedance SYxe2x80x94FET* of the output impedance SYxe2x80x94FET of the front-stage amplifying element 3, and an optimum input source impedance xcex93optxe2x80x94in, of the rear-stage amplifying element 4 agrees with a conjugate complex impedance SXxe2x80x94FET* of the input impedance SXxe2x80x94FET of the rear-stage amplifying element 4.
Therefore, in cases where a conjugate complex impedance matching is performed at an output terminal X of the front-stage amplifying element 3, as shown in FIG. 2(b), the inter-stage matching circuit 6 is designed so as to perform an impedance transformation from the input impedance SXxe2x80x94FET of the rear-stage amplifying element 4 to the conjugate complex impedance SYxe2x80x94FET* of the output impedance SYxe2x80x94FET of the front-stage amplifying element 3.
Also, in cases where a conjugate complex impedance matching is performed at an input terminal Y of the rear-stage amplifying element 4, as shown in FIG. 2(c), the inter-stage matching circuit 6 is designed so as to perform an impedance transformation from the output impedance SYxe2x80x94FET of the front-stage amplifying element 3 to the conjugate complex impedance SXxe2x80x94FET (=xcex93optxe2x80x94in) of the input impedance SXxe2x80x94FET of the rear-stage amplifying element 4.
Therefore, in cases where no loss occurs in the inter-stage matching circuit 6, when the conjugate complex impedance matching is performed at the output terminal X of the front-stage amplifying element 3, the conjugate complex impedance matching can be performed at the input terminal Y of the rear-stage amplifying element 4 simultaneously with the conjugate complex impedance matching at the output terminal X.
However, a level of the input signal transmitted through the multistage amplifier induces the conventional multistage amplifier to perform a large signal operation in a final-stage amplifying element or an amplifying element just before the final-stage amplifying element of the conventional multistage amplifier in place of the small signal operation.
In this case, the output impedance SYxe2x80x94FET of the front-stage amplifying element 3 and the input impedance SXxe2x80x94FET of the rear-stage amplifying element 4 in the large signal operation of the conventional multistage amplifier differ from those in the small signal operation, and optimum impedances, which maximize an efficiency of the conventional multistage amplifier, differ from the input and output impedances SXxe2x80x94FET and SYxe2x80x94FET. Therefore, in the large signal operation, the optimum output load impedance xcex93optxe2x80x94out of the front-stage amplifying element 3 differs from the conjugate complex impedance SYxe2x80x94FET* of the output impedance SYxe2x80x94FET of the front-stage amplifying element 3, and the optimum input source impedance xcex93optxe2x80x94in of the rear-stage amplifying element 4 differs from the conjugate complex impedance SXxe2x80x94FET* of the input impedance SXxe2x80x94FET of the rear-stage amplifying element 4.
Therefore, in cases where a conjugate complex impedance matching is performed at the output terminal X of the front-stage amplifying element 3, as shown in FIG. 2(b), the inter-stage matching circuit 6 is designed so as to perform an impedance transformation from the input impedance SXxe2x80x94FET of the rear-stage amplifying element 4 to the optimum output load impedance xcex93optxe2x80x94out (xe2x89xa0SXxe2x80x94FET*) of the front-stage amplifying element 3. Also, in cases where a conjugate complex impedance matching is performed at the input terminal Y of the rear-stage amplifying element 4, as shown in FIG. 2(c), the inter-stage matching circuit 6 is designed so as to perform an impedance transformation from the output impedance SYxe2x80x94FET of the front-stage amplifying element 3 to the optimum input source impedance xcex93optxe2x80x94in (≈SXxe2x80x94FET*) of the rear-stage amplifying element 4.
In this case, it is impossible for the inter-stage matching circuit 6 to perform the conjugate complex impedance matching at the output terminal X of the front-stage amplifying element 3 simultaneously with the conjugate complex impedance matching at the input terminal Y of the rear-stage amplifying element 4.
Because the conventional multistage amplifier has the above described configuration, it is impossible to perform the matching of the output load impedance Fout of the front-stage amplifying element 3 with the optimum output load impedance xcex93optxe2x80x94out simultaneously with the matching of the input source impedance Fin of the rear-stage amplifying element 4 with the optimum input source impedance xcex93optxe2x80x94in. Therefore, a problem has arisen that an efficiency of the whole conventional multistage amplifier is lowered.
The present invention is provided to solve the above-described problem, and the object of the present invention is to provide a multistage amplifier in which an output load impedance of a front-stage amplifying element and an input source impedance of a rear-stage amplifying element are simultaneously matched with optimum impedances respectively.
A multistage amplifier according to the present invention has a matching circuit comprising a one-stage high pass filter type matching unit and a one-stage low pass filter type matching unit serially connected with the one-stage high pass filter type matching unit.
Therefore, because an output load impedance of a front-stage amplifying element and an input source impedance of a rear-stage amplifying element can be matched with the optimum impedances respectively, an efficiency of the whole multistage amplifier can be heightened.
In the multistage amplifier according to the present invention, the matching circuit arranged between the final-stage amplifying element and the amplifying element placed just before the final-stage amplifying element comprises the one-stage high pass filter type matching unit and the one-stage low pass filter type matching unit serially connected with each other.
Therefore, a small-sized multistage amplifier can be obtained.
In the multistage amplifier according to the present invention, the one-stage high pass filter type matching unit is placed on an input side of the input signal, and the one-stage low pass filter type matching unit is placed on an output side of the amplified signal.
Therefore, an output load impedance of a front-stage amplifying element and an input source impedance of a rear-stage amplifying element can be watched with the optimum impedances respectively.
In the multistage amplifier according to the present invention, the one-stage low pass filter type matching unit is placed on an input side of the input signal, and the one-stage high pass filter type matching unit is placed on an output side of the amplified signal.
Therefore, an output load impedance of a front-stage amplifying element and an input source impedance of a rear-stage amplifying element can be matched with the optimum impedances respectively.
In the multistage amplifier according to the present invention, the one-stage high pass filter type matching unit comprises a parallel inductor and a serial capacitor.
Therefore, a small-sized one-stage high pass filter type matching unit can be obtained.
In the multistage amplifier according to the present invention, a bias supply short stub having a length equal to or shorter than xc2xc of a wavelength of the input signal is used as the parallel inductor.
Therefore, because the bias supply short stub can be used as a bias supply line on an output side of the front-stage amplifying element, a small-sized multistage amplifier can be obtained.
In the multistage amplifier according to the present invention, the one-stage low pass filter type matching unit comprises a parallel capacitor and a serial inductor.
Therefore, a small-sized one-stage low pass filter type matching unit can be obtained.
In the multistage amplifier according to the present invention, a serial line is used as the serial inductor.
Therefore, a small-sized one-stage low pass filter type matching unit can be obtained.